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// IP VLNV: xilinx.com:module_ref:adc_capture_module:1.0
// IP Revision: 1

`timescale 1ns/1ps

(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_adc_capture_module_0_0 (
  adc_input,
  adc_clk,
  reset_n,
  test_out,
  debug_status,
  debug_status2,
  debug_status3,
  M_AXIS_ACLK,
  M_AXIS_ARESETN,
  M_AXIS_TVALID,
  M_AXIS_TDATA,
  M_AXIS_TSTRB,
  M_AXIS_TLAST,
  M_AXIS_TREADY
);

input wire [7 : 0] adc_input;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME adc_clk, FREQ_HZ 5000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 adc_clk CLK" *)
input wire adc_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME reset_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset_n RST" *)
input wire reset_n;
output wire test_out;
output wire [7 : 0] debug_status;
output wire [7 : 0] debug_status2;
output wire [1 : 0] debug_status3;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET M_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXIS_ACLK CLK" *)
input wire M_AXIS_ACLK;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_AXIS_ARESETN RST" *)
input wire M_AXIS_ARESETN;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire M_AXIS_TVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] M_AXIS_TDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TSTRB" *)
output wire [3 : 0] M_AXIS_TSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire M_AXIS_TLAST;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 1, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire M_AXIS_TREADY;

  adc_capture_module #(
    .C_M_AXIS_TDATA_WIDTH(32),
    .C_M_START_COUNT(32),
    .CAPTURE_STATUS_STOP(8'B00000001),
    .CAPTURE_STATUS_CAPTURING(8'B00000000),
    .CAPTURE_STATUS_SEND_START(8'B00000010),
    .SEND_STATUS_STOP(8'B00000001),
    .SEND_STATUS_SENDING(8'B00000000),
    .SEND_STATUS_SEND_START(8'B00000010),
    .SEND_STATUS_IDLE(8'B00000011),
    .BUFFER_STATUS_FULL(8'B00000000),
    .BUFFER_STATUS_SENDING(8'B00000010),
    .BUFFER_STATUS_CAPTURING(8'B00000011),
    .BUFFER_STATUS_EMPTY(8'B00000100)
  ) inst (
    .adc_input(adc_input),
    .adc_clk(adc_clk),
    .reset_n(reset_n),
    .test_out(test_out),
    .debug_status(debug_status),
    .debug_status2(debug_status2),
    .debug_status3(debug_status3),
    .M_AXIS_ACLK(M_AXIS_ACLK),
    .M_AXIS_ARESETN(M_AXIS_ARESETN),
    .M_AXIS_TVALID(M_AXIS_TVALID),
    .M_AXIS_TDATA(M_AXIS_TDATA),
    .M_AXIS_TSTRB(M_AXIS_TSTRB),
    .M_AXIS_TLAST(M_AXIS_TLAST),
    .M_AXIS_TREADY(M_AXIS_TREADY)
  );
endmodule
